50 lines
2.0 KiB
JavaScript
50 lines
2.0 KiB
JavaScript
/*
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Language: VHDL
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Author: Igor Kalnitsky <igor@kalnitsky.org>
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Contributors: Daniel C.K. Kho <daniel.kho@gmail.com>
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Description: VHDL is a hardware description language used in electronic design automation to describe digital and mixed-signal systems.
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*/
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function(hljs) {
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return {
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case_insensitive: true,
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keywords: {
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keyword:
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'abs access after alias all and architecture array assert attribute begin block ' +
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'body buffer bus case component configuration constant context cover disconnect ' +
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'downto default else elsif end entity exit fairness file for force function generate ' +
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'generic group guarded if impure in inertial inout is label library linkage literal ' +
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'loop map mod nand new next nor not null of on open or others out package port ' +
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'postponed procedure process property protected pure range record register reject ' +
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'release rem report restrict restrict_guarantee return rol ror select sequence ' +
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'severity shared signal sla sll sra srl strong subtype then to transport type ' +
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'unaffected units until use variable vmode vprop vunit wait when while with xnor xor',
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typename:
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'boolean bit character severity_level integer time delay_length natural positive ' +
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'string bit_vector file_open_kind file_open_status std_ulogic std_ulogic_vector ' +
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'std_logic std_logic_vector unsigned signed boolean_vector integer_vector ' +
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'real_vector time_vector'
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},
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illegal: '{',
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contains: [
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hljs.C_BLOCK_COMMENT_MODE, // VHDL-2008 block commenting.
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{
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className: 'comment',
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begin: '--', end: '$'
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},
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hljs.QUOTE_STRING_MODE,
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hljs.C_NUMBER_MODE,
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{
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className: 'literal',
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begin: '\'(U|X|0|1|Z|W|L|H|-)\'',
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contains: [hljs.BACKSLASH_ESCAPE]
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},
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{
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className: 'attribute',
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begin: '\'[A-Za-z](_?[A-Za-z0-9])*',
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contains: [hljs.BACKSLASH_ESCAPE]
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}
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]
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};
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}
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